Synth: Open-Source Physical Design for Hardware That Starts as Code

Hardware should be programmable all the way down

Software engineers can describe a system, compile it, test it, inspect the errors, and iterate. Hardware design still too often begins with a blank schematic canvas, a large component library, and a long chain of manual translation between intent, connectivity, placement, routing, and manufacturing files.

Today we are open-sourcing Synth, our first step toward a programmable physical-design stack for electronics. Synth is a compact hardware description language and compiler for expressing boards, components, connections, constraints, and manufacturing intent as source code.

Alongside it, we are previewing Synth-EE: a cockpit for exploring what happens when an agent can work with that source, call design tools, inspect compiler and KiCad diagnostics, and iteratively improve a board.

Synth core: a small language with a concrete output

Synth is deliberately readable. A board can be described with components and explicit connectivity:

board "sensor_node" {
  layers 4
  manufacturer "jlcpcb"

  component U1: mcu "rp2350"
  component U2: secure_element "atecc608"
  component C1: capacitor "c_generic_0603"

  connect U1.vdd_io -> C1.p1
  connect U1.gp0 -> U2.sda
}

The important part is not the syntax by itself. The source is a durable, reviewable design contract. The compiler can resolve parts, check connectivity, derive an intermediate representation, route what it can, and emit real KiCad artifacts for further inspection and manufacturing workflows.

From source to KiCad

Synth is designed to work with the tools engineers already use. Its output is intended to be opened and checked in KiCad, where the resulting schematic and PCB can be inspected at native fidelity rather than treated as a decorative preview.

The render above is a native KiCad board render from the Synth design workflow, fitted to the actual board extents. It shows the direction we are pursuing: components, copper, silkscreen references, and board geometry should remain visible and auditable throughout the process.

The 3D view is also generated from the KiCad board artifact, including the board outline, footprints, copper, and silkscreen. It is useful as a quick physical sanity check while the native KiCad files remain the source of truth.

Synth-EE: an agent that can show its work

Synth-EE is the experimental layer on top. The goal is not to ask a model to guess a finished PCB in one response. The goal is to give it a disciplined engineering loop:

1. translate a natural-language requirement into a typed design intent;
2. generate or revise Synth source;
3. compile and inspect structured diagnostics;
4. use constrained repairs for syntax, topology, placement, and routing issues;
5. preserve each step, artifact, and decision for review;
6. export only when the design passes the required gates.

This separation matters. Synth remains useful as a compiler and language even when no model is involved. Synth-EE can then use the compiler as a feedback-rich environment, much like a programming agent uses a language compiler and test suite.

The cockpit is intentionally shown as a preview: it makes the run history, source, diagnostics, and board views visible in one place. Synth-EE is still evolving, but the workflow demonstrates the product direction without asking readers to treat an agent-generated board as automatically production-ready.

---

Where Synth sits in the landscape

Synth is not trying to replace traditional EDA tools. KiCad, Altium, and their peers are mature, capable desktop environments for engineers who need a manual drafting workflow — and KiCad in particular is the tool Synth treats as its primary interoperability target: Synth’s native output is the KiCad file format. Traditional EDA tools are where the design goes to be inspected, refined, and manufactured. Synth sits upstream of them.

The more relevant comparison is with a newer category: tools that position AI as a hardware design assistant. These fall into a few distinct patterns.

The browser schematic editor with AI suggestions

Several tools in this space offer a browser-native schematic editor and have added AI features — autocomplete for component search, routing hints, or a chat panel that proposes changes to the schematic. The design artifact is still fundamentally a GUI schematic: a visual graph that a human draws and an AI nudges.

The problem is not that AI assistance is unhelpful. It is that the schematic is not a stable artifact for the AI to operate on. When the AI suggests a change, it is typically expressed as a natural-language response that the engineer then applies manually. The design and the AI’s understanding of it can diverge. There is no compiler between the suggestion and the board.

Synth’s position: the .synth source file is the design artifact. The AI writes to it, the compiler validates it, and the result is inspectable before any geometry is committed.

The requirement-to-module selector

Another pattern: the tool accepts high-level requirements (power budget, connectivity, target chip family) and selects or configures existing reference modules or subsystems. The output is a pre-validated module combination rather than a from-scratch board.

This is useful for constrained product families where the design space is well-defined. It is less useful for custom embedded designs, novel sensor integrations, or boards that do not fit an existing module footprint.

Synth’s position: the language is general-purpose across board topologies. The compiler validates connectivity and design rules regardless of how the design was produced, not against a pre-approved module set.

The closed-loop AI PCB generator

A third pattern: the tool claims to generate a routed, manufacturable board from a natural-language prompt in one step. The output is typically a rendered image or a proprietary design file with no structured intermediate representation. There is no compiler. There are no structured diagnostics. The board is either accepted as-is or the process starts over.

This is the approach Synth is most directly structured against. Engineering judgment does not disappear because AI is involved — it gets delegated to a system that may not be able to express what it did or why. A board with no inspectable intermediate artifacts and no structured diagnostic path is difficult to audit, difficult to repair, and difficult to trust.

Synth’s position: every step has a typed representation. The compiler produces machine-readable diagnostics with source locations and repair hints. The agent is not the authority on whether a design is valid — the compiler is.

---

The comparison in brief

	Browser AI schematic editor	Module selector	AI PCB generator	Synth
Design artifact	Visual schematic (GUI)	Module spec	Rendered image	Text source (SynthSpec)
AI role	Suggestions in editor	Module matching	Board generation	Source generation + repair
Compiler validation	No	Against module set	No	Yes — structured JSON diagnostics
Machine-readable ERC/DRC	No	Partial	No	Yes
Open source	No	No	No	Yes (Apache 2.0)
KiCad interoperability	Partial	No	No	Native export target
Agent MCP interface	No	No	No	Yes

Traditional EDA tools (the open-source and commercial desktop editors) belong in a different row entirely — they are the downstream environment Synth produces output for, not a category Synth competes with.

---

Why open source it now?

Physical design is too important to hide behind a generated image or a proprietary black box. We want the language, compiler behavior, output artifacts, and failure modes to be inspectable by the people who will rely on them.

Synth is an early project. The compiler and KiCad export path are active work, and Synth-EE is a preview rather than a promise that every board can already be generated autonomously. That is exactly why we are opening the work now: real hardware projects, real compiler errors, and real scrutiny will make the system better.

What we are building toward

The longer-term direction is a complete, testable loop for electronics design:

• a stable and teachable Synth language;
• first-class compiler diagnostics with actionable repair hints;
• part-registry expansion with provenance and review;
• constraint-aware placement, board sizing, and routing;
• KiCad-native schematic, PCB, 3D, and fabrication outputs;
• durable agent runs that can be resumed, audited, and reproduced;
• human approval at the points where engineering judgment is required.

The model should be able to help with the work, but the compiler and design artifacts must remain the source of truth.

Try it and follow along

Synth core is open source and available for experimentation today. Synth-EE is being developed alongside it as we work toward a useful agentic hardware-design workflow.

• Synth core: GitHub
• Synth-EE preview: Product page
• Abstract Machines: absmach.eu

If you build with Synth, find a compiler edge case, or have a view on how agents should participate in hardware design, we would like to hear from you.